Design and implementation of high power, high linearity stacked RF FET switches in a 250 nm silicon on sapphire process

The RF circuitry in new generation mobile handsets is continuously becoming smaller while containing more functionality. Silicon-on-sapphire (SOS) technology is an advanced active device process that eases the fabrication of advanced wireless components on very high resistivity substrates. This paper presents the basic theory and resulting trade-offs regarding RF FET switches in order to achieve a high power handling capability, low insertion loss and high linearity of the latter. A combined RF switch consisting of eight stacked FETs, used in a high power switched capacitor banks, is designed with an insertion loss of 1 dB at 2 GHz for a transmitter power of 39.5 dBm. The presented configuration has a high linearity featuring P_1dB and IIP3 of 49.2 dBm and 54.3 dBm, respectively.