An efficient MOS VLSI timing simulator on parallel computers

A new timing simulator for MOS VLSI circuits has been developed. It is capable of performing accurate transient analysis, simulating large circuits, and improving the simulation speed. For simulating tightly coupled circuits, floating capacitors are used, and accuracy can be preserved. an efficient subcircuit model with latency exploitation is employed to reduce the simulation time. Benchmark tests on multiprocessors show that the simulation speed is about an order of speed faster than that of single CPUs for a number of circuits