Title :
Low power 5 GHz voltage-controlled oscillator using negative resistance enhancement technique
Author :
Hsu, Meng-Ting ; Wu, Hung-Sheng
Author_Institution :
Dept. & Inst. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Douliou, Taiwan
Abstract :
In this paper, we present low phase noise and low power of the voltage-controlled oscillators (VCOs) for 5 GHz applications. This chip is implemented by Taiwan Semiconductor Manufacturing Company (TSMC) standard 0.18μm CMOS process. The designed circuit topology is included a modified conventional pmos cross couple configuration. It is adopted pseudo resistance and using negative resistance enhancement technique. At the supply voltage 1v, the measured output phase noise is -120.13 dBc/Hz at 1MHz offset frequency from the carrier frequency of 5.47 GHz. The core power consumption is 2.65 mW, and tuning range of frequency is about 900MHz, from 4.68 to 5.58 GHz. The chip area is 0.754×0.544 (mm2).
Keywords :
CMOS integrated circuits; MMIC oscillators; field effect MMIC; integrated circuit noise; low-power electronics; negative resistance circuits; network topology; phase noise; voltage-controlled oscillators; TSMC standard CMOS process; Taiwan Semiconductor Manufacturing Company; VCO; carrier frequency; circuit topology; frequency 5 GHz; frequency tuning range; low phase noise oscillator; low power voltage-controlled oscillator; modified pMOS cross-couple configuration; negative resistance enhancement technique; offset frequency; output phase noise; power consumption; pseudoresistance; size 0.18 mum; voltage 1 V; CMOS integrated circuits; Microwave integrated circuits; Phase noise; Resistance; Semiconductor device measurement; Voltage-controlled oscillators; Low power; Negative resistance enhancement; Phase noise; Voltage-controlled oscillator (VCO);
Conference_Titel :
Microwave Conference Proceedings (APMC), 2011 Asia-Pacific
Conference_Location :
Melbourne, VIC
Print_ISBN :
978-1-4577-2034-5
