Title :
A methodology for automated behavioral verification of floating-point designs
Author :
Kannappan, Karthk ; Herbeck, Gilbert H. ; Stearns, C.
Author_Institution :
LSI Logic, Milpitas, CA, USA
Abstract :
Behavioral verification of hardware designs confirms that the input/output relationship of the circuit agrees with its specification. This involves simulations of the circuits and the software code that models the hardware. Key issues in such simulations are the generation of test vectors and creation of models. A methodology that automates behavioral verification of floating-point (fp) designs is described. Tools developed to generate test vectors (vecgen) and the models (fpc) and their roles in the verification process are discussed. The methodology has been used successfully on a large number of fp designs over a short period of time
Keywords :
automatic testing; digital arithmetic; logic CAD; logic testing; automated behavioral verification; floating-point designs; fp designs; hardware designs; input/output relationship; test vectors; verification process; Circuit simulation; Circuit testing; Flexible printed circuits; Graphics; Hardware; Kernel; Large scale integration; Logic design; Silicon; Software testing;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270216
