Reconfigurable and efficient FFT/IFFT architecture

Hardware or firmware implementations of fast Fourier transforms are found in many digital signal processing applications. However, most commercially available FFT/IFFT firmware cores lack reconfigurability, thus impeding reuse and increasing cost, design time, etc. The proposed FFT/IFFT core addresses those issues. It is parameterizable, flexible, and scalable at the design time. The resources needed for an FPGA implementation are comparable to the ones required by non-reconfigurable cores and significantly fewer than those required by available reconfigurable cores. Finally, the design allows real-time processing of a serial input signal, while adding minimal processing latency and optimizing memory usage.