Title :
Using high level design models for generation of test vectors
Author_Institution :
Hitachi America Ltd., Brisbane, CA
Abstract :
A description of a method using high-level design simulation that allows the use of functional timing simulations for test vector generation, while observing tester timing requirements is described. This method gives the designer the option of rapidly converting the design verification simulation modules in order to generate test vectors to the timing requirements of the targeted tester
Keywords :
automatic testing; logic CAD; logic testing; design verification simulation modules; functional timing simulations; high level design models; test vector generation; tester timing requirements; Artificial intelligence; Clocks; Costs; Delay; Design methodology; Discrete event simulation; Frequency; Production systems; System testing; Timing;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270222
