Title :
An 8×8 discrete cosine transform model using VHDL
Author :
Chen, Wei-chun ; Fan, Yimu ; Hsu, Kenneth W.
Author_Institution :
Dept. of Comput. Eng., Rochester Inst. of Technol., NY, USA
Abstract :
VHSIC hardware description language (VHDL) models are used to simulate a two-dimensional 8×8 discrete cosine transform (DCT) chip. Models are created and simulated in two levels: a behavioral model and a structural model. The whole system is verified by Mentor Graphics VHDL and constructed in true single phase clock (TSPC) logic
Keywords :
circuit analysis computing; digital signal processing chips; discrete cosine transforms; image processing; specification languages; 2D DCT chip; 8×8 configuration; DSP; Mentor Graphics; TSPC logic; VHDL; VHSIC hardware description language; behavioral model; discrete cosine transform model; structural model; true single phase clock; Arithmetic; Concurrent computing; Delay; Discrete cosine transforms; Documentation; Equations; Frequency; Read only memory;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270223
