Author :
Lu, Shih-Lien ; Merani, Lalit
Author_Institution :
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
Abstract :
Digital computation systems based on transition signal framework have many advantages. The synthesis of a self-timed physical design from a high-level dataflow specification is examined. The approach maps tokens that travel on data and control arcs of a dataflow graph into transitions of the event signals. The two-phase event signal transition style is employed, where both the rising edge and the trailing edge may represent the arrival of a token. The detailed designs of all seven primitives of a dataflow graph are presented
Keywords :
circuit analysis computing; logic CAD; parallel processing; pipeline processing; synchronisation; VHDL modelling; dataflow graph; high-level dataflow specification; micropipelines; self-timed physical design; two-phase event signal transition style; Circuits; Clocks; Control system synthesis; Delay; Digital systems; Distributed computing; Parallel processing; Signal synthesis; Synchronization; Timing;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270230
