The Impact of Interference on Multi-Level-Cell Applications in Scaled Nitride-Storage Flash Memory

Coupling interference from adjacent cells of conventional floating gate structure has become a main limiting factor of the scalability of NAND-type flash memory (J. Lee et al., 2002). The better immunity against the interference issue is always considered as the advantage of nitride-storage flash memory, which has been another mainstream of non-volatile memory because of its easy integration and the two-bit storage capability (B. Eitan, et al., 2000), (W.J. Tsai et al., 2001). However, it has been disclosed that the similar interference still exists in nitride-storage memory as wordlines become close enough (Y.W. Cheng et al., 2007). In this paper, the interference is further investigated in the programmed cells and it was demonstrated that the interference enlarges first and then diminishes as the programming level of the interfered bit increases. Such special turnaround interference will play an important role on the window definition for MLC (multi-level-ell) applications.