Title :
Improvement of TANOS NAND Flash Performance by the Optimization of a Sealing Layer
Author :
Breuil, L. ; Furnémont, A. ; Rothschild, A. ; Van den Bosch, G. ; Cacciato, A. ; Houdt, J. Van
Author_Institution :
IMEC, Leuven
Abstract :
We presented an optimization of an interfacial SiO2 sealing layer between the nitride and top dielectric of a TANOS stack showing a strong retention improvement thanks to an increased DeltaEc to Si3N4, that prevents vertical escape of the electrons through the top dielectric. In case of HfAlO top dielectric, it also provides a better program/disturb margin.
Keywords :
NAND circuits; flash memories; NAND flash performance; TANOS stack; interfacial sealing layer; top dielectric; Aluminum oxide; Electron traps; Etching; Hafnium; High K dielectric materials; High-K gate dielectrics; Oxidation; SONOS devices; Temperature; Voltage;
Conference_Titel :
Non-Volatile Semiconductor Memory Workshop, 2008 and 2008 International Conference on Memory Technology and Design. NVSMW/ICMTD 2008. Joint
Conference_Location :
Opio
Print_ISBN :
978-1-4244-1546-5
Electronic_ISBN :
978-1-4244-1547-2
DOI :
10.1109/NVSMW.2008.44
