Title :
BAT: an ASIC I/O interface analysis and synthesis tool
Author :
Nguyen, Ho T. ; Chiang, David R. ; Miller, Judy F.
Author_Institution :
AT&T Bell Lab., Allentown, PA, USA
Abstract :
A buffer analysis tool (BAT) that produces an electrical model of the chip interface, given an I/O buffer placement and the package type of the device, is described. BAT can estimate the peak switching ground noise voltage for a given configuration. Alternatively, if the I/O pin order is flexible, the tool can also synthesize an optimum pin order that will result in minimum switching noise voltage based on this estimation
Keywords :
application specific integrated circuits; buffer circuits; circuit CAD; circuit analysis computing; digital integrated circuits; ASIC I/O interface; BAT; I/O buffer placement; buffer analysis tool; chip interface; electrical model; minimum switching noise voltage; optimum pin order; package type; peak switching ground noise voltage; synthesis tool; Application specific integrated circuits; Circuit noise; Circuit simulation; Computational modeling; Guidelines; Noise generators; Noise level; Packaging; Pins; Voltage;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270242
