3-D interconnect capacitance calculation for multi-conductor and its application to a ROM circuit design

Two-dimensional and three-dimensional capacitance simulators have been developed for evaluating the parasitic capacitance in VLSI structures. The coupling capacitance, the cross-wiring capacitance, and the fringing capacitance between wires in a multilayer structure are studied. The application of the simulated interconnect capacitance to a ROM circuit shows that good match between simulation and experiments has been achieved. The scaling effect of a commercialized ROM circuit design is studied, from which a density of twice the original memory cell size can be obtained by the same design rule