DocumentCode
1607387
Title
Advanced delay analysis method for submicron ASIC technology
Author
Chung, Eui-Young ; Joo, Byung-Ha ; Lee, Young-Keun ; Kim, Kyung-Ho ; Lee, Sang-Hoon
Author_Institution
Samsung Electron., Kyung Ki-Do, South Korea
fYear
1992
Firstpage
471
Lastpage
474
Abstract
A new ASIC delay analysis method is presented, in which a two-dimensional delay table model is used for cells and the tailored circuit simulation is used for wires. Input waveform slope and load capacitance play important roles in the variation of cell delay. In the case of an arbitrary RC tree load, the equivalent load capacitance is calculated by using a node reduction technique and the proposed equation. This model preserves accurate delay estimation, typically within 3% compared to that of HSPICE
Keywords
application specific integrated circuits; circuit analysis computing; delays; digital integrated circuits; integrated circuit technology; RC tree load; circuit simulation; delay analysis method; delay estimation; load capacitance; node reduction technique; submicron ASIC technology; two-dimensional delay table model; Application specific integrated circuits; Capacitance; Circuit simulation; Delay estimation; Delay lines; Equations; Product development; Propagation delay; Telephony; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0768-2
Type
conf
DOI
10.1109/ASIC.1992.270245
Filename
270245
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