Title :
16 Kbit BiCMOS compilable gate array RAM with 2.5 ns access time
Author :
Yonemoto, Ryuji ; Enomoto, Yoshinori ; Watara, Katsuhiko
Author_Institution :
Fujitsu Microelectronics Inc., San Jose, CA, USA
Abstract :
A 2.5-ns dual-port BiCMOS SRAM compiler has been designed for a 0.8-μm 160 K sea-of-gates array. An autoadjusting precharge pulse generator was devised to ensure optimum access time for all RAM sizes and operating conditions. RAMs up to 32 kb can be constructed by using this compiler
Keywords :
BiCMOS integrated circuits; SRAM chips; cellular arrays; 0.8 micron; 16 Kbit; 2.5 ns; autoadjusting precharge pulse generator; compilable gate array RAM; dual-port BiCMOS SRAM compiler; sea-of-gates array; BiCMOS integrated circuits; Clocks; Decoding; Delay; Differential amplifiers; Pulse generation; Random access memory; Read-write memory; Timing; Voltage;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270250
