• DocumentCode
    1607521
  • Title

    A 473 K gate 0.7 μ CMOS gate array

  • Author

    Shiffer, Jim ; Brasen, Dan ; Hartoog, Mark ; Eastwick, Dave

  • Author_Institution
    COMPASS Design Autom., San Jose, CA, USA
  • fYear
    1992
  • Firstpage
    443
  • Lastpage
    446
  • Abstract
    A new gate array family has been created. The arrays are implemented in a 0.7-μm Leff process with either two or three metal layers. The largest array in the family has 473 K available gates. A high speed macro library which uses a four row architecture has been created for use with these arrays. Typical NAND gate delays are 230 ps. An improved power grid is implemented which does not interfere with macro placement, and which is routed by a power router
  • Keywords
    CMOS integrated circuits; cellular arrays; circuit layout CAD; logic CAD; logic arrays; 0.7 micron; 230 ps; CAD; NAND gate delays; four row architecture; gate array family; high speed macro library; macro placement; power router; Circuits; Large Hadron Collider; Routing; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
  • Conference_Location
    Rochester, NY
  • Print_ISBN
    0-7803-0768-2
  • Type

    conf

  • DOI
    10.1109/ASIC.1992.270251
  • Filename
    270251
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1607521