Title :
A 0.65 μm, low-voltage/low-power optimized CMOS gate array
Author :
Ko, Uming ; Schenck, Stephen ; Svejda, Frank ; La, Samuel
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
A 2.7-V to 3.6-V CMOS gate array with 0.65-μm effective gate length has been developed with an average power of 0.7 μW/gate/MHz and an inverter delay of 184 ps under two standard loads. The 3.3-V optimized compact base cell consists of two large and two small p- and n-channel transistors and achieves a density of one memory bit per base cell; typical memory access time is 7.3 ns. Library characteristics indicate 75% of device power can be conserved by decreasing the device supply voltage from 5 V to 3.3 V
Keywords :
CMOS integrated circuits; cellular arrays; circuit layout CAD; integrated memory circuits; logic CAD; logic arrays; 0.65 micron; 184 ps; 2.7 to 3.6 V; 7.3 ns; CMOS gate array; SOG memory compiler; inverter delay; library characteristics; low-power optimized; low-voltage; memory access time; sea of gates; Circuit testing; Clocks; Flip-flops; Logic circuits; Logic gates; Qualifications; Random access memory; Routing; Signal design; Voltage;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270252
