Embedded 6 bit flash converter design for digital stereo sound decoder

The design of a 25-MHz, 6-b flash converter embedded in a customized digital signal processor for decoding of digital stereo sound broadcast on terrestrial TV channels is described. The design is based upon an offset cancellation comparator which obviates the need for large storage capacitors traditionally used for input offset reduction, and makes the design easier to fabricate in standard CMOS technology. Simple measurement techniques used for design debug are described