Study of high level design methodologies for a MPEG frames I compressor for a HW/SW implementation

Time needed to set-up and send new products to the market is a crucial factor for success, so one important rule is to develop your product as quickly as you can. In the electronics world the systems normally contain some parts in HW and others in SW being the HW/SW partition a crucial issue in the cost-performance trade-off. A bad choice usually requires the redesign or remaps of some parts the system with the consequent waste of time and money. In the last years many new concepts appeared for the design of systems, with the called HW/SW co-design based on system (SoC) and virtual components. Those concepts rely to methodologies that try to integrate HW and SW design techniques in just one consistent system-level methodology allowing to work in a way that is more secure (specifications and developments are verifiable), more efficient (cost analysable) and that can be automated (through systems synthesis). Demonstrator based MPEG video compression has been designed and validated. It implements video coding using the standard ISO/IEC 13818-2 I ITU-T H.262H (also know as "MPEG2 Video"), for the main profile at main level (720×480, 30 fps). The encoder implements frames I or I-pictures.