Author :
Arnaud, F. ; Duriez, B. ; Tavel, B. ; Pain, L. ; Todeschini, J. ; Jurdit, M. ; Laplanche, Y. ; Boeuf, F. ; Salvetti, F. ; Lenoble, D. ; Reynard, J.P. ; Wacquant, F. ; Morin, P. ; Emonet, N. ; Barge, D. ; Bidaud, M. ; Ceccarelli, D. ; Vannier, P. ; Loquet,
Abstract :
A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 μm2 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully working 0.5 μm2 bit-cells with 240mV of SNM and 35 μA of cell current at 1.2V operation were obtained. The GP transistor drive currents of 875 μA/ μm and 400 μA/ μm for NMOS and PMOS respectively are obtained at Vdd = 1V, Ioff = 100nA/um. Using the same CMOS flow, 65nm analog transistor parameters are derived for the first time, showing Vt matching (Avt=2.2mV. μm) and analog voltage gain factor (Gm/Gd>2000 for L = 10 μm) at the leading edge for this process technology. NBTI criteria at 125°C for both LP and GP transistors are presented and characterized at overdrive conditions.
Keywords :
CMOS integrated circuits; SRAM chips; 1.2 V; 240 mV; 65 nm; SRAM bit-cells; analog transistor parameters; low cost 65nm CMOS platform; transistor drive currents; CMOS process; CMOS technology; Costs; Dielectric substrates; Etching; MOS devices; Niobium compounds; Random access memory; Silicon; Voltage;
