Title :
The use of bit conserving logic in design for testability
Author :
Gribble, Barry R. ; Aylor, James H. ; Jones, Stephen H. ; Johnson, Bany W.
Author_Institution :
Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
Abstract :
A method of design for testability (DFT) and built-in self-test (BIST) based upon bit conserving logic ((BCL) is presented. This method is completely general and requires only two function-independent input test vectors for 100% testing of single stuck-at faults regardless of the size of complexity of the circuit. Both combinational and sequential circuits can be tested with no scan techniques
Keywords :
built-in self test; combinatorial circuits; design for testability; logic design; logic testing; sequential circuits; (BCL; BIST; DFT; bit conserving logic; built-in self-test; combinational circuits; design for testability; function-independent input test vectors; sequential circuits; single stuck-at faults; Built-in self-test; Circuit faults; Circuit testing; Costs; Design for testability; Electrical fault detection; Logic circuits; Logic design; Logic testing; Manufacturing processes;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270265
