Transistor optimization for leakage power management in a 65 nm CMOS technology for wireless and mobile applications

Author

Zhao, S. ; Chatterjee, A. ; Tang, S. ; Yoon, J. ; Crank, S. ; Bu, H. ; Houston, T. ; Sadra, K. ; Jain, A. ; Wang, Y. ; Redwine, D. ; Chen, Y. ; Siddiqui, S. ; Zhang, G. ; Laaksonen, T. ; Hall, C. ; Chang, S. ; Olsen, L. ; Riley, T. ; Meek, C. ; Hossain, I

Author_Institution

Silicon Tech. Dev., Texas Instrum. Inc., Dallas, TX, USA

fYear

2004

Firstpage

14

Lastpage

15

Abstract

This paper presents a transistor optimization methodology tailored for wireless, digital consumer, and mobile applications that employ power management circuit techniques. This methodology is applied to a 65nm technology that supports a high-density (<0.5 um²) embedded 6T SRAM cell. High performance logic (I_dn/I_dp = 550/300uA/um at L_poly = 39nm) and low leakage are achieved simultaneously by employing a data retention mode for the SRAM (I_leakage ∼2pA/bit). Retention mode bias conditions and selective gate sizing in the SRAM reduces leakage by ∼300X. Advanced transistor design including SSR channel, strain engineering, drain-extension (HDD) offset spacer, and HDD and halo profile optimization is used to achieve at least an additional 4× reduction in leakage.

Keywords

CMOS integrated circuits; VLSI; leakage currents; 65 nm; 65 nm CMOS technology; SRAM; advanced transistor design; data retention mode; halo profile optimization; leakage power management; mobile applications; transistor optimization; wireless applications; CMOS technology; Capacitive sensors; Circuits; Design engineering; Energy management; Logic; Optimization methods; Random access memory; Technology management; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8289-7

Type

conf

DOI

10.1109/VLSIT.2004.1345365

Filename

1345365