Four layer metal, flip chip, submicron ASIC product designed for advanced multichip module

Author

Grula, Jerry ; Blood, William

Author_Institution

Motorola Inc., Chandler, AZ, USA

fYear

1992

Firstpage

238

Lastpage

241

Abstract

The use of an additional metal layer on a large CMOS ASIC part provides a practical method for converting an existing chip design with wirebond or tape automated bonding (TAB) peripheral pads to an array of flip chip solder bumps across the chip surface. While there are advantages to single chip packages with flip chip interconnect, multichip modules are required to take full advantage of flip chip packing density and performance gains. Compared with single chip packages on a printed circuit board, flip chip multichip modules offer about a 10× surface area reduction. Propagation delays in signal interconnect lines are about three times faster for the module than single chip packages on a printed circuit board

Keywords

CMOS integrated circuits; application specific integrated circuits; flip-chip devices; multichip modules; packaging; tape automated bonding; CMOS; additional metal layer; advanced multichip module; flip chip solder bumps; packing density; performance gains; propagation delays; signal interconnect lines; submicron ASIC product; surface area reduction; tape automated bonding; wirebond; Application specific integrated circuits; Bonding; Chip scale packaging; Flip chip; Integrated circuit interconnections; Multichip modules; Performance gain; Printed circuits; Product design; Propagation delay;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0768-2

Type

conf

DOI

10.1109/ASIC.1992.270268

Filename

270268