Title :
Evaluation of test strategies for multichip modules
Author :
Lin, Ting-Ting Y. ; Comito, John ; Kaseff, Charles
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
Two parallel testing strategies for multichip modules-the boundary-scan technique and the cascadable built-in tester (CBIT)-are evaluated in terms of testing time, fault coverage, and area overhead. Results on a small-scale processor configuration favor the CBIT design for test effectiveness of the chip, and the boundary-scan design for area overhead interconnection tests
Keywords :
boundary scan testing; built-in self test; fault location; integrated circuit testing; multichip modules; production testing; CBIT design; area overhead; boundary-scan technique; cascadable built-in tester; fault coverage; interconnection tests; multichip modules; small-scale processor configuration; test strategies; testing time; Built-in self-test; Circuit testing; Clocks; Costs; Integrated circuit interconnections; Logic testing; Multichip modules; Packaging; Pins; Test pattern generators;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270269
