A VLSI implementation of an arithmetic coder for image compression

Arithmetic coding is an efficient data compression technique. This paper describes the VLSI implementation of an arithmetic coder for a multilevel alphabet (256 symbols). The design we propose is based on the use of redundant arithmetic and the development of new schemes for storing and updating the cumulative probabilities and updating the range and left point of the interval. The use of redundant arithmetic reduces the delays of the modules, so the speed of the design is improved. The resulting chip has an area of 31 mm/sup 2/ and a operating frequency of 39 MHz.