Title :
80 nm 512M DRAM with enhanced data retention time using partially-insulated cell array transistor (PiCAT)
Author :
Yeo, Kyoung Hwan ; Oh, Chang Woo ; Kim, Sung-Min ; Kim, Min-Sang ; Lee, Chang-Sub ; Lee, Sung-Young ; Li, Ming ; Cho, Hye-Jin ; Yoon, Enn-Jung ; Kim, Sung-Hwan ; Choe, Jeong-Dong ; Kim, Dong-Won ; Park, Donggun ; Kim, Kinam
Author_Institution :
ATD Team, Samsung Electron. Co., Kyunggi-Do, South Korea
Abstract :
An 80 nm 512M DDR DRAM with partially-insulated cell array transistor (PiCAT) was fabricated. Si/SiGe epitaxial growth and selective SiGe etch process were used to form PiOX (Partially-Insulating OXide) under source and drain of the cell transistor. Using these technologies, partial-SOI (Silicon-On-Insulator) structure could be realized with excellent structural and electrical advantages on bulk Si wafer. Self-limited shallow junction under source/drain and halo doping effect at the channel region were formed by PiOX. With PiCAT, junction leakage current and SCE (Short Channel Effect) were reduced, and excellent data retention time was obtained.
Keywords :
DRAM chips; Ge-Si alloys; VLSI; silicon; silicon-on-insulator; 512 Mbit; 80 nm; 80 nm 512M DRAM; Si-SiGe; Si/SiGe epitaxial growth; SiGe; enhanced data retention time; junction leakage current; partial-SOI; partially-insulated cell array transistor; selective SiGe etch process; self-limited shallow junction; Doping; Epitaxial layers; Etching; Germanium silicon alloys; Insulation; Leakage current; Random access memory; Silicon germanium; Substrates; Transistors;
Conference_Titel :
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8289-7
DOI :
10.1109/VLSIT.2004.1345375
