Title :
Development and simulation of a 4080-point Winograd fast Fourier transform processor
Author :
Scribner, Kenn ; Mehalic, Mark
Author_Institution :
Dept. of Electr. & Comput. Eng., Air Force Inst. of Technol., Wright-Patterson AFB, OH, USA
Abstract :
By using the Good-Thomas prime factor algorithm, 15-, 16-, and 17-point Winograd algorithm fast Fourier transform (FFT) processors are combined to perform 4080-point FFTs. The circuits are analyzed in VHSIC hardware description language (VHDL), simulated, and laid out in MAGIC for fabrication through MOSIS. The VHDL simulation includes behavioral modeling and the simulation of 15-, 16-, 17-, and 4080-point FFT problems. Two of the three FFT processors are submitted for fabrication using a 1.2-μm CMOS process
Keywords :
CMOS integrated circuits; digital signal processing chips; digital simulation; fast Fourier transforms; specification languages; 1.2 micron; 4080-point Winograd fast Fourier transform processor; CMOS process; Good-Thomas prime factor algorithm; MAGIC; MOSIS; VHSIC hardware description language; Winograd algorithm; behavioral modeling; Analytical models; CMOS process; Circuit analysis; Circuit simulation; Fabrication; Fast Fourier transforms; Flexible printed circuits; Hardware design languages; Semiconductor device modeling; Very high speed integrated circuits;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270276
