DocumentCode
1608271
Title
A JBIG arithmetic coder-decoder chip
Author
Tong, Po ; Ang, Peng
Author_Institution
LSI Logic Corp., Milpitas, CA, USA
fYear
1992
Firstpage
189
Lastpage
192
Abstract
A Joint Bilevel Image Experts Group (JBIG) arithmetic coder-decoder chip is presented. In addition to arithmetic coding, the chip also performs probability estimation for adaptation. With a 40-MHz clock, this half-duplex chip can process 8 Mb of raw data per second. The throughput is the same for both encode and decode operations, and is independent of the compression ratio. The chip is fabricated using a CMOS 1-μm compacted array technology. Tests indicate that the chip is fully functional
Keywords
CMOS integrated circuits; application specific integrated circuits; codecs; digital arithmetic; image coding; logic arrays; 1 micron; 40 MHz; CMOS; JBIG arithmetic coder-decoder chip; Joint Bilevel Image Experts Group; adaptation; compacted array technology; compression ratio; decode operations; encode operations; half-duplex chip; probability estimation; Arithmetic; CMOS technology; Clocks; Codecs; Decoding; Image coding; Large scale integration; Logic; Testing; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0768-2
Type
conf
DOI
10.1109/ASIC.1992.270280
Filename
270280
Link To Document