Title :
Silicon assembler design of a DCT/IDCT ASIC for real-time JPEG/MPEG compression
Author :
Kocher, M. ; Rose, K.
Author_Institution :
Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
Abstract :
A single multiplier skewed pipeline architecture is presented for real time computation of the 1D discrete cosine transform (DCT)/IDCT in a 2-μm process. This architecture is extended to the 2-D case using a single 1-D DCT module by an appropriate choice of algorithm. Silicon compilation techniques are used, and the design of three module generators is examined
Keywords :
application specific integrated circuits; data compression; discrete cosine transforms; image coding; image processing equipment; pipeline processing; 1D transforms; 2 micron; 2D transforms; DCT/IDCT ASIC; assembler design; discrete cosine transform; module generators; real time computation; real-time JPEG/MPEG compression; silicon compilation; skewed pipeline architecture; Application specific integrated circuits; Assembly; Computer architecture; Discrete cosine transforms; Image coding; Latches; Programmable logic arrays; Read-write memory; Silicon; Transform coding;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270281
