Systematic study of pFET Vt with Hf-based gate stacks with poly-Si and FUSI gates

The flatband/threshold voltages (V_fb/V_t) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO₂ at poly-Si deposition temperatures is identified as the root cause for the poor V_fb/V_t control. No improvement in V_t control is obtained by engineering physically closed Si₃N₄ barrier layers on HfO₂. It is furthermore shown for the first time that even when the gate is fully silicided (FUSI) large V_fb/V_t shifts are observed with HfO₂. Reduced pFET shifts are observed when Hf-silicates with low Hf content are used and further improvements are observed by using Al₂O₃ cap layers on silicates.