DocumentCode
1608352
Title
Synthesized self-timed synchronous systems
Author
Auletta, Richard J.
Author_Institution
George Mason Univ., Fairfax, VA, USA
fYear
1992
Firstpage
175
Lastpage
178
Abstract
Communicating sequential processes (CSP) is used as the specification language for the synthesis of self-timed synchronous circuits. VHSIC hardware description language (VHDL) is used as the intermediate representation for synthesis with existing logic and high level synthesis tools. This approach preserves the functional properties of the CSP specification while allowing temporal properties to be enforced within the digital domain
Keywords
VLSI; integrated logic circuits; logic CAD; specification languages; CSP specification; VHSIC hardware description language; communicating sequential processes; digital domain; functional properties; high level synthesis tools; self-timed synchronous circuits; specification language; temporal properties; Circuit synthesis; Digital circuits; Flexible printed circuits; Hardware; High level synthesis; Logic circuits; Protocols; Resource management; Specification languages; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0768-2
Type
conf
DOI
10.1109/ASIC.1992.270283
Filename
270283
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