Bit-flip injection strategies for FSMs modeled in VHDL behavioral level

Author

Espinosa-Duran, John M. ; Trujillo-Olaya, Vladimir ; Velasco-Medina, Jaime ; Velazco, Raoul

Author_Institution

Sch. of Electr. & Electron. Eng., Univ. del Valle, Cali, Colombia

fYear

2010

Firstpage

1

Lastpage

5

Abstract

This paper presents two strategies to inject bit-flips in FSMs modeled in VHDL behavioral level. The dependability validation to SEUs or MEUs into the FSM flip flops is carried out by means of minor modifications on the VHDL description. The simulation results show that the proposed strategies have a low area overhead, allow synchronous and asynchronous fault injection and are very suitable to carry out the dependability validation step on FSMs.

Keywords

finite state machines; flip-flops; hardware description languages; radiation hardening (electronics); FSM flip flops; VHDL behavioral level; area overhead; asynchronous fault injection; bit-flip injection strategies; dependability validation; finite state machines; single event upsets; Circuit faults; Encoding; Fault tolerance; Fault tolerant systems; Radiation detectors; Registers; Simulation; Bit-flip injection; VHDL behavioral description; dependability validation; radiation effects;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Workshop (LATW), 2010 11th Latin American

Conference_Location

Pule del Este

Print_ISBN

978-1-4244-7786-9

Electronic_ISBN

978-1-4244-7785-2

Type

conf

DOI

10.1109/LATW.2010.5550340

Filename

5550340