DocumentCode :
1608475
Title :
Balance in architectural design
Author :
Ho, Samuel ; Snyder, Lawrence
Author_Institution :
Washington Univ., Seattle, WA, USA
fYear :
1990
Firstpage :
302
Lastpage :
310
Abstract :
A performance metric, normalized time, which is closely related to such measures as the area-time product of VLSI theory and the price/performance ratio of advertising literature is introduced. This metric captures the idea of a piece of hardware `pulling its own weight´, that is, contributing as much to performance as it costs in resources. The authors prove general theorems for stating when the size of a given part is in balance with its utilization and give specific formulas for commonly found linear and quadratic devices. They also apply these formulas to an analysis of a specific processor element and discuss the implications for bit-serial-versus-word-parallel, RISC-versus-CISC (reduced-versus complex-instruction-set-computer), and VLIW (very-long-instruction-word) designs
Keywords :
computer architecture; performance evaluation; RISC-versus-CISC; VLIW; architectural design; bit-serial-versus-word-parallel; normalized time; performance metric; processor element; Art; Concurrent computing; Contracts; Costs; Design engineering; Hardware; Independent component analysis; Parallel machines; Performance loss; Reduced instruction set computing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture, 1990. Proceedings., 17th Annual International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-8186-2047-1
Type :
conf
DOI :
10.1109/ISCA.1990.134539
Filename :
134539
Link To Document :
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