Tutorial on design for testability

Author

Shastry, Nanjunda

Author_Institution

Vertex Semicond. Corp., San Jose, CA, USA

fYear

1992

Firstpage

139

Lastpage

142

Abstract

Testability must be incorporated in all phases of an ASIC design, including wafer level, chip level, I/O level, and board/system level. Level-sensitive scan design (LSSD) is a design technique that uses latches and flip-flops that are level sensitive as opposed to edge triggered. The basic approach of LSSD is to make a sequential network appear like combinatorial logic during testing by logically eliminating feedback loops. LSSD, scan techniques, boundary scan requirements (IEEE 1149.1), and built-in self test (BIST) concepts for memories are described

Keywords

application specific integrated circuits; boundary scan testing; built-in self test; design for testability; integrated circuit testing; sequential circuits; ASIC design; I/O level; LSSD; board/system level; boundary scan requirements; built-in self test; chip level; design for testability; flip-flops; latches; scan techniques; sequential network; wafer level; Application specific integrated circuits; Automatic testing; Built-in self-test; Design for testability; Feedback loop; Flip-flops; Logic testing; Sequential analysis; System testing; Tutorial;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0768-2

Type

conf

DOI

10.1109/ASIC.1992.270291

Filename

270291