DocumentCode
1608547
Title
Testability measure and analysis
Author
Reddy, Pratapa V C V
Author_Institution
Dept. of Comput. & Electr. Eng., Rochester Inst. of Technol., NY, USA
fYear
1992
Firstpage
129
Lastpage
138
Abstract
Testability is a major concern in the design of VLSICs and ASICs. Testing can be simplified and made more effective if design for testability (DFT) techniques are incorporated into the design. There are many methods to analyze, measure, and evaluate the effectiveness of a DFT technique. A review of some of the widely used methods for measuring testability is presented
Keywords
VLSI; application specific integrated circuits; design for testability; integrated circuit testing; logic testing; ASICs; VLSICs; design for testability; testability measure; Automatic testing; Circuit faults; Circuit testing; Costs; Design for testability; Digital systems; Logic testing; Sequential analysis; System testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0768-2
Type
conf
DOI
10.1109/ASIC.1992.270292
Filename
270292
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