Title :
A standard cell set for delay insensitive VLSI design
Author :
Antognetti, Paolo ; Danielli, Paolo ; De Gloria, Alessandro ; Faraboschi, Paolo ; Oliveri, M.
Author_Institution :
Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
Abstract :
Delay insensitive circuits can solve several problems of VLSI designs. A synthesis system that automatically generates delay insensitive circuits from behavioral specifications has been developed by means of connection of dedicated standard cells. The electrical characterization of the standard cell set is presented, with emphasis on the new aspects introduced by this field of VLSI design. Complexity and speed parameters of each cell are reported. A first example of layout obtained by the system is present and evaluated
Keywords :
VLSI; cellular arrays; integrated logic circuits; logic CAD; VLSI design; behavioral specifications; dedicated standard cells; delay insensitive VLSI design; electrical characterization; layout; speed parameters; standard cell set; Character generation; Circuit synthesis; Clocks; Delay effects; Design engineering; Frequency synthesizers; Standards development; Threshold voltage; Very large scale integration; Wires;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270293
