Title :
An optimised FPGA configuration for signal processing
Author :
Baka, M.E. ; Copping, A.J.
Author_Institution :
Centre for Commun. Res., Bristol Univ., UK
Abstract :
A field programmable gate array (FPGA) configuration for digital filtering operations is described. The FPGA is configured as a linear systolic array of logical macrocells in which data are broadcast locally and operated on rhythmically. Templates have been created defining macrocells. Each macrocell is made of a fixed number of configurable layer blocks (CLBs) which could be reconfigured to optimize performance. The logical macrocell structure and the connection topology are examined
Keywords :
digital filters; digital signal processing chips; logic arrays; systolic arrays; configurable layer blocks; connection topology; digital filtering operations; linear systolic array; local broadcast; logical macrocell structure; logical macrocells; optimised FPGA configuration; rhythmic operation; templates; Delay; Digital filters; Field programmable gate arrays; Filtering; Finite impulse response filter; Logic arrays; Macrocell networks; Programmable logic arrays; Signal processing; Systolic arrays;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270297
