DocumentCode
1608839
Title
Split-gate NAND flash memory at 120nm technology node featuring fast programming and erase
Author
Cheng-Yuan Hsu ; Hung, Chi-Wei ; Sung, Da ; Wu, Chi-Shan ; Chen, S.C. ; Kuo, H.H. ; Pan, J.Y. ; Chen, C.L. ; Chuang, I.C. ; Huang, Vincent ; Hsue, C.C. ; Fan, Der-Tsyr ; Lu, Jung-Chang ; Cho, Caleb Y -S ; Tseng, Kevin ; Hsu, Annie ; Sheen, Ben ; Tuntasood
Author_Institution
PowerChip Semicond. Corp., Hsin-Chu, Taiwan
fYear
2004
Firstpage
78
Lastpage
79
Abstract
For the first time, split-gate NAND flash memory featuring interpoly erase and mid-channel programming is demonstrated at 120nm technology node. The cell array operates at single polarity voltages lower than 12V. Erase and programming can be accomplished in 0.5ms and 10μs, respectively.
Keywords
VLSI; flash memories; logic gates; nanotechnology; 0.5 ms; 10 mus; 12 V; 120 nm; 120nm technology node; erase; fast programming; single polarity voltages; split-gate NAND flash memory; Character generation; Electrons; Etching; Flash memory; Flash memory cells; Low voltage; Split gate flash memory cells; Throughput; Tunneling; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN
0-7803-8289-7
Type
conf
DOI
10.1109/VLSIT.2004.1345403
Filename
1345403
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