Layout synthesis of combinational blocks from behavioral hardware descriptions

Author

Wu, Qinghong ; Ramírez-Chávez, Sergio R.

Author_Institution

Dept. of Electr. Eng., Bucknell Univ., Lewisburg, PA, USA

fYear

1992

Firstpage

38

Lastpage

41

Abstract

A CAD tool that generates the layout of a combinational circuit from a behavioral hardware description language (HDL) representation is presented. A minimized transistor netlist is synthesised. Simulated annealing is used to determine the optimal placement and routing of each transistor group. As input, the system accepts VHSIC hardware description language (VHDL), VERILOG, truth table, and Boolean equation descriptions. For simulation purposes SPICE models of the circuit are also generated

Keywords

SPICE; circuit layout CAD; combinatorial circuits; logic CAD; network routing; simulated annealing; specification languages; Boolean equation; CAD tool; SPICE models; VERILOG; VHSIC hardware description language; behavioral hardware descriptions; combinational blocks; minimized transistor netlist; optimal placement; routing; simulated annealing; transistor group; truth table; CMOS technology; Circuit simulation; Circuit synthesis; Circuit topology; Combinational circuits; Equations; Hardware design languages; Routing; SPICE; Simulated annealing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0768-2

Type

conf

DOI

10.1109/ASIC.1992.270311

Filename

270311