Title :
Physical synthesis for performance optimization
Author :
Pokala, Rao R. ; Feretich, Robert A. ; Mcguffin, Roy W.
Author_Institution :
Vertex Semicond., San Jose, CA, USA
Abstract :
Three physical synthesis tools that improve the performance and routability of high-end gate array ASICs are described. The first tool orders scan rings efficiently after placement. The second tool groups single-bit flip-flops into multiple-bit hard-wired flip-flops macros in order to reduce clock delays and skews. The third tool commutes nets to improve performance without affecting functionality
Keywords :
circuit layout CAD; clocks; flip-flops; logic CAD; logic arrays; network routing; clock delays; high-end gate array ASICs; multiple-bit hard-wired flip-flops macros; performance; performance optimization; physical synthesis tools; placement; routability; scan rings; single-bit flip-flops; Application specific integrated circuits; Automatic testing; Clocks; Delay; Flip-flops; Logic arrays; Logic design; Logic testing; Optimization; Routing;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270312
