Title :
Timing driven placement of pads and latches
Author :
Chen, B. ; Marek-Sadowska, M.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
A heuristic approach to the placement of I/O pads and sequential elements prior to the layout of a VLSI circuit is presented. The input information for the algorithm is the structure of the circuit and its path delay constraints. Experimental results suggest that the loss in performance can be substantial (on the order of 10%) when pads and/or latches are placed without consideration of performance.<>
Keywords :
VLSI; circuit layout CAD; flip-flops; integrated logic circuits; logic CAD; sequential circuits; I/O pads; VLSI circuit; heuristic approach; latches; path delay constraints; performance loss; sequential elements; timing-driven placement; Algorithm design and analysis; Atherosclerosis; Circuits; Clocks; Delay; Gravity; Latches; Performance loss; Timing; Very large scale integration;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY, USA
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270313
