65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application

Author

Fung, Samuel K H ; Huang, H.T. ; Cheng, S.M. ; Cheng, K.L. ; Wang, S.W. ; Wang, Y.P. ; Yao, Y.Y. ; Chu, M. ; Yang, S.J. ; Liang, W.J. ; Leung, Y.K. ; Wu, C.C. ; Lin, C.Y. ; Chang, S.J. ; Wu, S.Y. ; Nieh, C.F. ; Chen, C.C. ; Lee, T.L. ; Jin, Y. ; Chen, S.C

Author_Institution

R&D, Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan

fYear

2004

Firstpage

92

Lastpage

93

Abstract

This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm / 45nm and <40nm gate length transistor at EOT 1.95nm / 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1 A and drive current is increased by 7%.

Keywords

CMOS integrated circuits; power MOSFET; rapid thermal annealing; 1 A; 1.2 nm; 1.4 nm; 1.95 nm; 300 mm; 40 nm; 45 nm; 55 nm; 65 nm; 65nm CMOS; Laser Spike Anneal; gate activation dose; high volume foundry application; optimized gate height; power transistor technology; thermal cycle reduction; Annealing; CMOS technology; Degradation; Doping; Foundries; Manufacturing; Power transistors; Robust stability; Space technology; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8289-7

Type

conf

DOI

10.1109/VLSIT.2004.1345411

Filename

1345411