Title :
Minimum skew multiple clock routing in synchronous ASIC systems
Author :
Khan, Waseem ; Hossain, Moazzem ; Sherwani, Naveed
Author_Institution :
Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
Abstract :
The problem of routing in the multiple clock environment is more complicated than a single clock environment. An efficient algorithm to obtain minimum skew layout for two clocks in a synchronous system is presented. The algorithm is tested on several industrial benchmarks with promising results. The routing layouts achieve almost zero skew, while using a minimum wire length for multiple clock routing
Keywords :
application specific integrated circuits; circuit layout CAD; clocks; digital integrated circuits; logic CAD; network routing; industrial benchmarks; minimum skew layout; minimum wire length; multiple clock routing; routing layouts; synchronous ASIC systems; synchronous system; Application specific integrated circuits; Benchmark testing; Circuit testing; Clocks; Delay effects; Logic; Minimization; Routing; Very large scale integration; Wire;
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270315
