Zero-skew clock routing trees with minimum wirelength

Author

Boese, Kenneth D. ; Kahng, Andrew B.

Author_Institution

Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA

fYear

1992

Firstpage

17

Lastpage

21

Abstract

The deferred-merge embedding (DME) algorithm is presented. In linear time, it embeds any given connection topology into the Manhattan plane to create a clock tree with zero skew while minimizing total wirelength. Experimental results show that the algorithm yields exact zero skew trees with 9% to 16% wirelength reduction over previous constructions. The DME algorithm may be applied to either the Elmore or the linear delay model and yields optimal total wirelength for linear delay

Keywords

VLSI; application specific integrated circuits; circuit layout CAD; clocks; digital integrated circuits; logic CAD; network topology; trees (mathematics); wiring; Elmore delay model; Manhattan plane; clock routing trees; connection topology; deferred-merge embedding; linear delay model; linear time; minimum wirelength; optimal total wirelength; wirelength reduction; zero skew trees; Circuits; Clocks; Delay effects; Delay lines; Minimization; Propagation delay; Routing; Synchronization; Topology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0768-2

Type

conf

DOI

10.1109/ASIC.1992.270316

Filename

270316