Title :
Impact of mechanical stress engineering on flicker noise characteristics
Author :
Maeda, Shigenobu ; Jin, You-Seung ; Choi, Jung-A ; Oh, Sun-Young ; Lee, Hyun-Woo ; Yoo, Jae-Yoon ; Sun, Min-Chul ; Ku, Ja-Hum ; Lee, Kwon ; Bae, Su-Gou ; Kang, Sung-Gun ; Yang, Jeong-Hwan ; Kim, Young-Wug ; Suh, Kwang-Pyuk
Author_Institution :
Syst. LSI Div., Samsung Electron. Co. Ltd., Yongin, South Korea
Abstract :
Relationship between mechanical stress engineering and flicker noise are clarified for the first time using a 50nm level CMOS technology. It is found that enhanced mechanical stress degrades flicker noise characteristics. Trap states and dipoles generated by the stress are considered to be the cause of degradation. The transistor performance enhancement with flicker noise reduction by nitrogen profile optimization in gate dielectric is demonstrated as a countermeasure.
Keywords :
CMOS integrated circuits; flicker noise; integrated circuit noise; stress effects; 50 nm; 50nm level CMOS technology; dipoles; flicker noise characteristics; gate dielectric; mechanical stress engineering; trap states; 1f noise; CMOS technology; Compressive stress; Degradation; Frequency; Large scale integration; MOS devices; MOSFETs; Scattering; Tensile stress;
Conference_Titel :
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8289-7
DOI :
10.1109/VLSIT.2004.1345417
