DocumentCode
1609217
Title
Reliability analysis of small delay defects in vias located in signal paths
Author
Villacorta, Hector ; Champac, Victor ; Hawkins, Chuck ; Segura, Jaume
Author_Institution
Dept. of Electron. Eng., Nat. Inst. for Astrophys., Opt. & Electron.-INAOE, Puebla, Mexico
fYear
2010
Firstpage
1
Lastpage
6
Abstract
Vias-open defects are one of the dominant failures in modern nanometer technologies and may pose a reliability issue. In this paper, the reliability electromigration risk posed by undetected small delays due to resistive opens in vias located in signal paths is quantified. The Mean Time to Failure as function of the void size, using a cylinder model for the defective via, is estimated. Both effects, electromigration and self heating, have been considered. Reliability analysis considering redundant vias is also presented.
Keywords
electromigration; integrated circuit reliability; dominant failures; modern nanometer technologies; reliability analysis; reliability electromigration risk; self heating; small delay defects; vias-open defects; Current density; Delay; Electromigration; Integrated circuit interconnections; Metals; Reliability; Resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Workshop (LATW), 2010 11th Latin American
Conference_Location
Pule del Este
Print_ISBN
978-1-4244-7786-9
Electronic_ISBN
978-1-4244-7785-2
Type
conf
DOI
10.1109/LATW.2010.5550366
Filename
5550366
Link To Document