• DocumentCode
    1609225
  • Title

    Development of a FPGA-based high speed FFT processor for wideband Direction of Arrival applications

  • Author

    Jamali, Mohsin ; Downey, Joseph ; Wilikins, Nathan ; Rehm, Christopher R. ; Tipping, Joseph

  • Author_Institution
    EECS Dept., Univ. of Toledo, Toledo, OH
  • fYear
    2009
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A parallel and pipelined Fast Fourier Transform (FFT) processor for use in the Direction of Arrival (DOA) estimation of a wideband waveform is presented. The selected DOA algorithm follows the Coherent Signal Subspace Method (CSSM). The target device for implementation is a Xilinx Virtex-5 Field Programmable Gate Array (FPGA). The FFT processor was developed in MATLAB Simulink using the Xilinx System Generator block-set to auto-generate VHDL code. Although the parallel and pipelined architecture uses a large portion of the available FPGA resources, the architecture does yield a high throughput.
  • Keywords
    direction-of-arrival estimation; fast Fourier transforms; field programmable gate arrays; hardware description languages; high-speed techniques; passive radar; radar computing; radar signal processing; DOA estimation; FPGA-based high speed FFT processor; MATLAB Simulink; VHDL code; Xilinx Virtex-5 field programmable gate array; coherent signal subspace method; fast Fourier transform; parallel architecture; passive radar system; pipelined architecture; wideband direction of arrival application; Antenna arrays; Covariance matrix; Direction of arrival estimation; Field programmable gate arrays; Passive radar; Radar antennas; Radar scattering; Sensor arrays; Signal processing algorithms; Wideband;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Radar Conference, 2009 IEEE
  • Conference_Location
    Pasadena, CA
  • ISSN
    1097-5659
  • Print_ISBN
    978-1-4244-2870-0
  • Electronic_ISBN
    1097-5659
  • Type

    conf

  • DOI
    10.1109/RADAR.2009.4977061
  • Filename
    4977061