Design and performance analysis of low power ternary ADC for wide band communication

Author

Jayashree, H.V. ; Harsha, K. ; Kaushik, M. ; Anusha, K. ; Divya, B.M.

Author_Institution

Dept. of E&C, PES Inst. of Technol., Bangalore, India

fYear

2014

fDate

4-5 April 2014

Firstpage

24

Lastpage

29

Abstract

This paper presents the design architectures of two digit and three digit ternary analog to digital converters (T-ADC), and compares their performance with their respective binary counterparts. The T-ADC is designed using analog comparators and ternary CMOS logic gates. It is proved that a two digit ternary ADC performs better over a three bit binary ADC in terms of power consumption and dynamic range. Thus, a T-ADC proves to be a better choice when used in wide band communication applications.

Keywords

analogue-digital conversion; low-power electronics; T-ADC; analog comparators; design architectures; dynamic range; low power ternary ADC; performance analysis; power consumption; ternary CMOS logic gates; three digit ternary analog to digital converters; two digit ternary analog to digital converters; wideband communication; Analog-digital conversion; CMOS integrated circuits; Information technology; Inverters; Logic gates; Quantization (signal); Resistors; comparator; encoder; high resolution; step size; ternary ADC;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits, Systems, Communication and Information Technology Applications (CSCITA), 2014 International Conference on

Conference_Location

Mumbai

Type

conf

DOI

10.1109/CSCITA.2014.6839229

Filename

6839229