Design and performance analysis of low power ternary ADC for wide band communication

This paper presents the design architectures of two digit and three digit ternary analog to digital converters (T-ADC), and compares their performance with their respective binary counterparts. The T-ADC is designed using analog comparators and ternary CMOS logic gates. It is proved that a two digit ternary ADC performs better over a three bit binary ADC in terms of power consumption and dynamic range. Thus, a T-ADC proves to be a better choice when used in wide band communication applications.