DocumentCode
1609370
Title
Notice of Violation of IEEE Publication Principles
Time minimization of hybrid BIST for systems-on-chip
Author
Popa, I. ; Cazacu, D.
Author_Institution
Electron. & Comput. Dept., Univ. of Pitesti, Pitesti, Romania
fYear
2008
Firstpage
153
Lastpage
158
Abstract
Notice of Violation of IEEE Publication Principles
"Time Minimization of hybrid BIST for systems-on-chip"
by I. Popa, D. Cazacu
in the 31st International Spring Seminar on Electronics Technology (ISSE 2008), 2008, pp. 153 - 158
After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE\´s Publication Principles.
This paper contains significant portions of original text from the paper cited below. The original text was copied with insufficient attribution (including appropriate references to the original author(s) and/or paper title) and without permission.
Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:
"Test Time Minimization for Hybrid BIST of Core-Based Systems"
by Gert Jervan, Petru Eles, Zebo Peng, Raimun Ubar, Maksim Jenihhin
in the 12th IEEE Asian Test Symposium (ATS03), 2003, pp. 318 - 323
\n\n\t\t
"Time Minimization of hybrid BIST for systems-on-chip"
by I. Popa, D. Cazacu
in the 31st International Spring Seminar on Electronics Technology (ISSE 2008), 2008, pp. 153 - 158
After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE\´s Publication Principles.
This paper contains significant portions of original text from the paper cited below. The original text was copied with insufficient attribution (including appropriate references to the original author(s) and/or paper title) and without permission.
Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:
"Test Time Minimization for Hybrid BIST of Core-Based Systems"
by Gert Jervan, Petru Eles, Zebo Peng, Raimun Ubar, Maksim Jenihhin
in the 12th IEEE Asian Test Symposium (ATS03), 2003, pp. 318 - 323
Keywords
built-in self test; circuit optimisation; design for testability; integrated circuit testing; system-on-chip; build-in-self-test; hybrid BIST optimization; multicore design; pseudorandom pattern generator; system-on-chip; test architecture; test-per-clock; test-per-scan application scheme; Built-in self-test; Circuit testing; Costs; Design optimization; Logic testing; Memory management; Minimization; Nondestructive testing; System testing; Test pattern generators; BIST; Build-In-Self-Test (BIST); Design-For-Test (DFT); Test Pattern Generator (TPG);
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Technology, 2008. ISSE '08. 31st International Spring Seminar on
Conference_Location
Budapest
Print_ISBN
978-1-4244-3972-0
Type
conf
DOI
10.1109/ISSE.2008.5276515
Filename
5276515
Link To Document