Direct measurement of stress dependent inversion layer mobility using a novel test structure

We propose a novel mobility measurement method which can be applied to industrial sized MOSFETs. The mobility variation caused by Shallow Trench Isolation (STI) stress is evaluated directly. Extracted piezoresistance coefficients in the inversion layer are close to their counterparts in bulk silicon. The stress effect model like that incorporated into BSIM4.3.0 is verified to adequately predict the behavior. Additionally, we have observed for the first time that the inversion layer mobility in <100> channel MOSFETs is less sensitive to the STI stress than that in <110> channel along MOSFETs. Therefore, CMOS devices with layouts the <100> direction is expected to have high performance with reduced source of design complication.