A methodology to characterize device-level endurance in 1T1C (1-transistor and 1-capacitor) FRAM

Author

Ahn, W.S. ; Jung, D.J. ; Hong, Y.K. ; Kim, H.H. ; Kang, S.K. ; Kang, Sung Kil ; Kim, J- H. ; Kim, Jong-Hyun ; Jung, J.Y. ; Jung, Jae Yun ; Ko, H.K. ; Choi, D.Y. ; Kim, Soo Youn ; Lee, Eun S. ; Kang, J.Y. ; Wei ; Lee ; A, K.H. ; Jung, H.S.

Author_Institution

Technology-Development Team 2, Semiconductor R&D center, Memory Division, Samsung Electronics Co. Ltd., San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Kyungki-Do, Korea

Volume

1

fYear

2008

Firstpage

1

Lastpage

4

Abstract

We present a mimicking methodology to describe device-level endurance in a 1T1C, 64 Mb FRAM (ferroelectric random access memory). Device-level endurance of FRAM must clarify all the issues raised from destructive read-out READ/WRITE. To explore endurance properties in a real-time operational situation, we have established a measurement set-up that covers asymmetric pulse chains corresponding to Data 1 (D1) and Data 0 (D0) READ/RESTORE over a frequency range from 1.0 to 7.7 MHz. The cycle-to-failure of 5.9 ?? 1024 cycles in an operational condition of 7.7 MHz and 85 ??C, has been obtained from extrapolation to VDD = 2.0 V in a voltage acceleration. We compare testing results with those of D1??D0 populations of bit-line potential.

Keywords

Acceleration; Extrapolation; Ferroelectric films; Ferroelectric materials; Frequency measurement; Nonvolatile memory; Pulse measurements; Random access memory; Testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Applications of Ferroelectrics, 2008. ISAF 2008. 17th IEEE International Symposium on the

Conference_Location

Santa Re, NM, USA

ISSN

1099-4734

Print_ISBN

978-1-4244-2744-4

Electronic_ISBN

1099-4734

Type

conf

DOI

10.1109/ISAF.2008.4693962

Filename

4693962